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authorChen-Yu Tsai <wens@csie.org>2014-07-09 11:54:39 +0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-07-15 10:54:16 +0400
commitdf02dd828c4ef2311c7c271f2c95384fc555961b (patch)
treea7f4110d273bb64662b96a524cacfdf27f9a0dd8 /arch/arm/boot/dts/sun8i-a23.dtsi
parentc571111ac1d6e99a4ad49ae105325704e3381ccc (diff)
downloadlinux-df02dd828c4ef2311c7c271f2c95384fc555961b.tar.xz
ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI
With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a23.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi47
1 files changed, 46 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 886776d09c06..54ac0787216a 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -285,13 +285,58 @@
interrupts = <1 9 0xf04>;
};
+ prcm@01f01400 {
+ compatible = "allwinner,sun8i-a23-prcm";
+ reg = <0x01f01400 0x200>;
+
+ ar100: ar100_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "ar100";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&ar100>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: apb0_clk {
+ compatible = "allwinner,sun8i-a23-apb0-clk";
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible = "allwinner,sun8i-a23-apb0-gates-clk";
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_pio", "apb0_timer",
+ "apb0_rsb", "apb0_uart",
+ "apb0_i2c";
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+ };
+
r_uart: serial@01f02800 {
compatible = "snps,dw-apb-uart";
reg = <0x01f02800 0x400>;
interrupts = <0 38 4>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb0_gates 4>;
+ resets = <&apb0_rst 4>;
status = "disabled";
};
};