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authorChen-Yu Tsai <wens@csie.org>2019-01-09 18:02:53 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-01-09 18:31:51 +0300
commit26e9ffeb2c04f0f577d0179e7eca8e1d54f9e050 (patch)
treefdf3bb22bcdfd59838cdec6c2358fdcaa43277ba /arch/arm/boot/dts/sun8i-r40.dtsi
parent09c6572290f018d73ec2e812e28bada34d41815f (diff)
downloadlinux-26e9ffeb2c04f0f577d0179e7eca8e1d54f9e050.tar.xz
ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup
UART3 on the PG pingroup on the R40 SoC is commonly used to connect the bluetooth controller in a WiFi+Bluetooth combo chip, with the WiFi bits also on the PG pingroup. This patch adds two device nodes for UART3 on PG pingroup, one for the RX/TX pins, and one for the RTS/CTS pins. Consumers can reference either just the RX/TX pinmux setting or both, depending on the application. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-r40.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-r40.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 89762dbefe42..f1fcfa0bdce0 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -389,6 +389,16 @@
pins = "PB22", "PB23";
function = "uart0";
};
+
+ uart3_pg_pins: uart3-pg-pins {
+ pins = "PG6", "PG7";
+ function = "uart3";
+ };
+
+ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
+ pins = "PG8", "PG9";
+ function = "uart3";
+ };
};
wdt: watchdog@1c20c90 {