summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/sun9i-a80-optimus.dts
diff options
context:
space:
mode:
authorChen-Yu Tsai <wens@csie.org>2016-01-21 08:26:41 +0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-01-25 02:01:21 +0300
commit02df9cb85e156924339f2244aec29dcc37d9ab8c (patch)
tree52ef35fe3698685775daf6cef53aa2605aa153c8 /arch/arm/boot/dts/sun9i-a80-optimus.dts
parent675ec62b08480fe1250c70cba61ad6e74652ed6f (diff)
downloadlinux-02df9cb85e156924339f2244aec29dcc37d9ab8c.tar.xz
ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC
mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80-optimus.dts')
-rw-r--r--arch/arm/boot/dts/sun9i-a80-optimus.dts6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c0060e4f7379..958160e40fd0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -174,9 +174,15 @@
vmmc-supply = <&reg_vcc3v0>;
bus-width = <8>;
non-removable;
+ cap-mmc-hw-reset;
status = "okay";
};
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_optimus>;
gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */