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authorLaxman Dewangan <ldewangan@nvidia.com>2013-03-15 22:37:25 +0400
committerStephen Warren <swarren@nvidia.com>2013-04-05 03:17:41 +0400
commit6ea0297e39139a777c826339761afb3603c72e10 (patch)
tree913da34172c476ee3f608cb0b2ebab511dffc282 /arch/arm/boot/dts/tegra114.dtsi
parentcd467b7d0c1eb5e8179ab47d56f4f6c5d0d4aa74 (diff)
downloadlinux-6ea0297e39139a777c826339761afb3603c72e10.tar.xz
ARM: tegra: add SPI nodes to Tegra114 DT
NVIDIA's Tegra114 has 6 SPI controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi", since they are a new incompatible design. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed reg property for 3rd SPI controller] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra114.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi72
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index f83399f62015..629415ffd8dc 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -217,6 +217,78 @@
status = "disabled";
};
+ spi@7000d400 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-request-selector = <&apbdma 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 41>;
+ clock-names = "spi";
+ status = "disabled";
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 44>;
+ clock-names = "spi";
+ status = "disabled";
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000d800 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-request-selector = <&apbdma 17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 46>;
+ clock-names = "spi";
+ status = "disabled";
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-request-selector = <&apbdma 18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 68>;
+ clock-names = "spi";
+ status = "disabled";
+ };
+
+ spi@7000dc00 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-request-selector = <&apbdma 27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 104>;
+ clock-names = "spi";
+ status = "disabled";
+ };
+
+ spi@7000de00 {
+ compatible = "nvidia,tegra114-spi";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-request-selector = <&apbdma 28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 105>;
+ clock-names = "spi";
+ status = "disabled";
+ };
+
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;