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authorTuomas Tynkkynen <ttynkkynen@nvidia.com>2015-05-13 17:58:45 +0300
committerThierry Reding <treding@nvidia.com>2015-08-21 19:44:24 +0300
commit9be1e477c31437907d0db4fa72d7c2920dfdeec8 (patch)
tree30ce424b4532837993093e0fa0b8614665976789 /arch/arm/boot/dts/tegra124-jetson-tk1.dts
parentbf9d026775796bec30895cab080baf37b70bc3b3 (diff)
downloadlinux-9be1e477c31437907d0db4fa72d7c2920dfdeec8.tar.xz
ARM: tegra: Enable the DFLL on the Jetson TK1
Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124-jetson-tk1.dts')
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index bd43ed6d6ec7..192111ac00b3 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1462,7 +1462,7 @@
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
- sd0 {
+ vdd_cpu: sd0 {
regulator-name = "+VDD_CPU_AP";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1400000>;
@@ -1694,6 +1694,13 @@
non-removable;
};
+ /* CPU DFLL clock */
+ clock@0,70110000 {
+ status = "okay";
+ vdd-cpu-supply = <&vdd_cpu>;
+ nvidia,i2c-fs-rate = <400000>;
+ };
+
ahub@0,70300000 {
i2s@0,70301100 {
status = "okay";