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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2018-09-02 13:08:44 +0300
committerThierry Reding <treding@nvidia.com>2018-09-26 17:55:12 +0300
commit992cf09b14e391748c46add889e4249603fa3a39 (patch)
tree36c21bc3bfe311641eb045ada143b5313476abed /arch/arm/boot/dts/tegra20-colibri-iris.dts
parenta2cb59be1086450c8dea7bfbbf2bf0e47c93ced1 (diff)
downloadlinux-992cf09b14e391748c46add889e4249603fa3a39.tar.xz
ARM: tegra: colibri_t20: add missing pinmux
Explicitly add pinmux' for all T20 SoC ball groups now: - Colibri Address/Data Bus (GMI) further pins used as GPIOs - Colibri BL_ON - Colibri EXT_IO* - Colibri L_BIAS, LCD_M1 is muxed with LCD_DE today's display need DE, disable LCD_M1 - more Colibri LCD pins (L_* resp. LDD<*>) - Colibri LCD (Optional 24 BPP Support) - Colibri MMCCD - uart_a_dsr and uart_a_dcd as GPIOs - Colibri USB_CDET - I2C3 (Optional) - JTAG_RTCK - LAN_RESET, LAN_EXT_WAKEUP and LAN_PME (All On-module) - more NAND pins - RESET_OUT - THERMD_ALERT# (On-module), unlatched I2C address pin of LM95245 temperature sensor therefore requires disabling for now Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-colibri-iris.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-iris.dts40
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index e026478b58d0..28386b89d910 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -29,6 +29,10 @@
pinmux@70000014 {
state_default: pinmux {
+ bl-on {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
ddc {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
@@ -37,10 +41,38 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+ i2c {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ lm1 {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
mmc {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+ mmccd {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ pwm-a-b {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ pwm-c-d {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ ssp {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
uart-a {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
@@ -48,6 +80,14 @@
uart-b {
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+
+ uart-c {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ usbh-pen {
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
};
};