summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/tegra20.dtsi
diff options
context:
space:
mode:
authorDmitry Osipenko <digetx@gmail.com>2018-12-12 23:38:50 +0300
committerJoerg Roedel <jroedel@suse.de>2019-01-16 15:54:11 +0300
commit334175243cc6b97aa7e846e623cc500e1d56a39c (patch)
treeaac3d0027318406e676e7a9905b17143780b8454 /arch/arm/boot/dts/tegra20.dtsi
parent53f986accf34d4428b90b26086b9571ea653b920 (diff)
downloadlinux-334175243cc6b97aa7e846e623cc500e1d56a39c.tar.xz
ARM: dts: tegra20: Update Memory Controller node to the new binding
Device tree binding of Memory Controller has been changed: GART has been squashed into the MC, there are a new mandatory clock and #iommu-cells properties, the compatible has been changed to 'tegra20-mc-gart'. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi15
1 files changed, 6 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index dcad6d6128cf..8c942e60703e 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -616,17 +616,14 @@
};
mc: memory-controller@7000f000 {
- compatible = "nvidia,tegra20-mc";
- reg = <0x7000f000 0x024
- 0x7000f03c 0x3c4>;
+ compatible = "nvidia,tegra20-mc-gart";
+ reg = <0x7000f000 0x400 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
+ clocks = <&tegra_car TEGRA20_CLK_MC>;
+ clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
- };
-
- iommu@7000f024 {
- compatible = "nvidia,tegra20-gart";
- reg = <0x7000f024 0x00000018 /* controller registers */
- 0x58000000 0x02000000>; /* GART aperture */
+ #iommu-cells = <0>;
};
memory-controller@7000f400 {