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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-08-28 21:27:42 +0300
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-08-30 15:13:13 +0300
commit3bdba5ac181a2e9eb76bb7673bb11ab5b9783f63 (patch)
treec9b6a0e7f1be7670c7dc5694bbfbaf2a7e8ac12c /arch/arm/boot/dts/uniphier-pxs2.dtsi
parent77896e4d05af6a9330c5410a4d45cc72fd030f1c (diff)
downloadlinux-3bdba5ac181a2e9eb76bb7673bb11ab5b9783f63.tar.xz
ARM: dts: uniphier: switch over to PSCI
Use PSCI for enable-method instead of SoC specific implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-pxs2.dtsi')
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2.dtsi5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 6d702d2d7757..63c12e8ea029 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -51,12 +51,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -64,6 +64,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -71,6 +72,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -78,6 +80,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
};