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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2014-09-03 01:19:08 +0400
committerMichal Simek <michal.simek@xilinx.com>2014-09-16 14:55:06 +0400
commit36ad5ae6dea7ae6abbb7bdf25078e7d1dabcecad (patch)
tree92749ae268e4de6a8942de1d7ef1f5f28d2c4fd7 /arch/arm/boot/dts/zynq-7000.dtsi
parentc07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d (diff)
downloadlinux-36ad5ae6dea7ae6abbb7bdf25078e7d1dabcecad.tar.xz
ARM: zynq: DT: Add DDRC node
Add the DDR controller to the Zynq devicetree. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6cc83d4c6c76..587cadcf7001 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -146,6 +146,11 @@
cache-level = <2>;
};
+ memory-controller@f8006000 {
+ compatible = "xlnx,zynq-ddrc-a05";
+ reg = <0xf8006000 0x1000>;
+ } ;
+
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";