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authorPeter Rosin <peda@axentia.se>2022-11-12 18:40:59 +0300
committerClaudiu Beznea <claudiu.beznea@microchip.com>2022-11-24 13:50:07 +0300
commit6a3fc8c330d1c1fa3d8773d7d38a7c55c4900dfe (patch)
tree5c0c7689fbdedd90d1fd3057983ccc2ff88b649d /arch/arm/mach-at91
parent40a2226e8bfacb79dd154dea68febeead9d847e9 (diff)
downloadlinux-6a3fc8c330d1c1fa3d8773d7d38a7c55c4900dfe.tar.xz
ARM: at91: fix build for SAMA5D3 w/o L2 cache
The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but apparently not for the older SAMA5D3. Solves a build-time regression with the following symptom: sama5.c:(.init.text+0x48): undefined reference to `outer_cache' Fixes: 3b5a7ca7d252 ("ARM: at91: setup outer cache .write_sec() callback if needed") Signed-off-by: Peter Rosin <peda@axentia.se> [claudiu.beznea: delete "At least not always." from commit description] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/b7f8dacc-5e1f-0eb2-188e-3ad9a9f7613d@axentia.se
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/sama5.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index 67ed68fbe3a5..bf2b5c6a18c6 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -26,7 +26,7 @@ static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
static void __init sama5_secure_cache_init(void)
{
sam_secure_init();
- if (sam_linux_is_optee_available())
+ if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())
outer_cache.write_sec = sama5_l2c310_write_sec;
}