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authorAnson Huang <Anson.Huang@nxp.com>2019-12-11 05:53:36 +0300
committerShawn Guo <shawnguo@kernel.org>2019-12-12 15:38:04 +0300
commit4562fa4c86c92a2df635fe0697c9e06379738741 (patch)
tree24fd39fa96c01a8111a739f5bd66b4196703d11c /arch/arm/mach-imx/Kconfig
parentb3082f1bf8a604c9a0f483b5d6060d7255c2a51b (diff)
downloadlinux-4562fa4c86c92a2df635fe0697c9e06379738741.tar.xz
ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D
ARM_ERRATA_814220 has below description: The v7 ARM states that all cache and branch predictor maintenance operations that do not specify an address execute, relative to each other, in program order. However, because of this erratum, an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable ARM_ERRATA_814220 for proper workaround. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/mach-imx/Kconfig')
-rw-r--r--arch/arm/mach-imx/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 593bf1519608..4326c8f53462 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -520,6 +520,7 @@ config SOC_IMX6UL
bool "i.MX6 UltraLite support"
select PINCTRL_IMX6UL
select SOC_IMX6
+ select ARM_ERRATA_814220
help
This enables support for Freescale i.MX6 UltraLite processor.
@@ -556,6 +557,7 @@ config SOC_IMX7D
select PINCTRL_IMX7D
select SOC_IMX7D_CA7 if ARCH_MULTI_V7
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
+ select ARM_ERRATA_814220
help
This enables support for Freescale i.MX7 Dual processor.