summaryrefslogtreecommitdiff
path: root/arch/arm/mach-lpc32xx
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2016-12-16 02:39:02 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2016-12-16 02:39:02 +0300
commite79ab194d15e1baa25540cb9efaf2a459cf4bc32 (patch)
tree3a2ec9280e286e531a5d18e255271db21368c2d7 /arch/arm/mach-lpc32xx
parent3ec5e8d82b1a4ee42c8956099d89b87917dd3ba5 (diff)
parent44c29b83de1770910b9f4d53bf78f6118da5165f (diff)
downloadlinux-e79ab194d15e1baa25540cb9efaf2a459cf4bc32.tar.xz
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files. Noteworthy changes include: - Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while. - Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family. - Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G - SMP is now supported on the OX820 platform - A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release - Davinci has some new work to improve USB support - For i.MX, the performance monitor now supports profiling the memory controller using 'perf'" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r--arch/arm/mach-lpc32xx/clock.h38
-rw-r--r--arch/arm/mach-lpc32xx/common.h1
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h117
-rw-r--r--arch/arm/mach-lpc32xx/pm.c1
4 files changed, 0 insertions, 157 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
deleted file mode 100644
index c0a8434307f7..000000000000
--- a/arch/arm/mach-lpc32xx/clock.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/clock.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __LPC32XX_CLOCK_H
-#define __LPC32XX_CLOCK_H
-
-struct clk {
- struct list_head node;
- struct clk *parent;
- u32 rate;
- u32 usecount;
-
- int (*set_rate) (struct clk *, unsigned long);
- unsigned long (*round_rate) (struct clk *, unsigned long);
- unsigned long (*get_rate) (struct clk *clk);
- int (*enable) (struct clk *, int);
-
- /* Register address and bit mask for simple clocks */
- void __iomem *enable_reg;
- u32 enable_mask;
-};
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 30c9e64fc65b..02575c2444e4 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -24,7 +24,6 @@
/*
* Other arch specific structures and functions
*/
-extern void __init lpc32xx_init_irq(void);
extern void __init lpc32xx_map_io(void);
extern void __init lpc32xx_serial_init(void);
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
deleted file mode 100644
index 00190535df90..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/irqs.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARM_ARCH_IRQS_H
-#define __ASM_ARM_ARCH_IRQS_H
-
-#define LPC32XX_SIC1_IRQ(n) (32 + (n))
-#define LPC32XX_SIC2_IRQ(n) (64 + (n))
-
-/*
- * MIC interrupts
- */
-#define IRQ_LPC32XX_SUB1IRQ 0
-#define IRQ_LPC32XX_SUB2IRQ 1
-#define IRQ_LPC32XX_PWM3 3
-#define IRQ_LPC32XX_PWM4 4
-#define IRQ_LPC32XX_HSTIMER 5
-#define IRQ_LPC32XX_WATCH 6
-#define IRQ_LPC32XX_UART_IIR3 7
-#define IRQ_LPC32XX_UART_IIR4 8
-#define IRQ_LPC32XX_UART_IIR5 9
-#define IRQ_LPC32XX_UART_IIR6 10
-#define IRQ_LPC32XX_FLASH 11
-#define IRQ_LPC32XX_SD1 13
-#define IRQ_LPC32XX_LCD 14
-#define IRQ_LPC32XX_SD0 15
-#define IRQ_LPC32XX_TIMER0 16
-#define IRQ_LPC32XX_TIMER1 17
-#define IRQ_LPC32XX_TIMER2 18
-#define IRQ_LPC32XX_TIMER3 19
-#define IRQ_LPC32XX_SSP0 20
-#define IRQ_LPC32XX_SSP1 21
-#define IRQ_LPC32XX_I2S0 22
-#define IRQ_LPC32XX_I2S1 23
-#define IRQ_LPC32XX_UART_IIR7 24
-#define IRQ_LPC32XX_UART_IIR2 25
-#define IRQ_LPC32XX_UART_IIR1 26
-#define IRQ_LPC32XX_MSTIMER 27
-#define IRQ_LPC32XX_DMA 28
-#define IRQ_LPC32XX_ETHERNET 29
-#define IRQ_LPC32XX_SUB1FIQ 30
-#define IRQ_LPC32XX_SUB2FIQ 31
-
-/*
- * SIC1 interrupts start at offset 32
- */
-#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
-#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
-#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
-#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
-#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
-#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
-#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12)
-#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13)
-#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14)
-#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17)
-#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18)
-#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19)
-#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20)
-#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22)
-#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23)
-#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24)
-#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25)
-#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26)
-#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27)
-#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28)
-#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29)
-#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30)
-#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31)
-
-/*
- * SIC2 interrupts start at offset 64
- */
-#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0)
-#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1)
-#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2)
-#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3)
-#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4)
-#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5)
-#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6)
-#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7)
-#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8)
-#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9)
-#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10)
-#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11)
-#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12)
-#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15)
-#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18)
-#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19)
-#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20)
-#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22)
-#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23)
-#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24)
-#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25)
-#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26)
-#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27)
-#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
-#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
-
-#define LPC32XX_NR_IRQS 96
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 207e81275ff0..62471570d586 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -73,7 +73,6 @@
#include <mach/hardware.h>
#include <mach/platform.h>
#include "common.h"
-#include "clock.h"
#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)