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author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-07-24 03:31:31 +0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-07-24 03:31:31 +0400 |
commit | f01b9b73f57f4f92d39bba0d9aa4a38f318212df (patch) | |
tree | b815a4477af34f7f6c61dff0c04db6cb975cdd55 /arch/arm/mach-mvebu/irq-armada-370-xp.c | |
parent | fde75430278130505cac21997cd9f90b7bb2670a (diff) | |
parent | 66314223aa5e862c9d1d068cb7186b4fd58ebeaa (diff) | |
download | linux-f01b9b73f57f4f92d39bba0d9aa4a38f318212df.tar.xz |
Merge tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull support for three new arm SoC types from Arnd Bergmann:
- The mvebu platform includes Marvell's Armada XP and Armada 370 chips,
made by the mvebu business unit inside of Marvell. Since the same
group also made the older but similar platforms we call "orion5x",
"kirkwood", "mv78xx0" and "dove", we plan to move all of them into
the mach-mvebu directory in the future.
- socfpga is Altera's platform based on Cortex-A9 cores and a lot of
FPGA space. This is similar to the Xilinx zynq platform we already
support. The code is particularly clean, which is helped by the fact
that the hardware doesn't do much besides the parts that are expected
to get added in the FPGA.
- The OMAP subarchitecture gains support for the latest generation, the
OMAP5 based on the new Cortex-A15 core. Support is rather
rudimentary for now, but will be extended in the future.
* tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits)
ARM: socfpga: initial support for Altera's SOCFPGA platform
arm: mvebu: generate DTBs for supported SoCs
ARM: mvebu: MPIC: read number of interrupts from control register
arm: mach-mvebu: add entry to MAINTAINERS
arm: mach-mvebu: add compilation/configuration change
arm: mach-mvebu: add defconfig
arm: mach-mvebu: add documentation for new device tree bindings
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
arm: mach-mvebu: add source files
arm: mach-mvebu: add header
clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver
ARM: Kconfig update to support additional GPIOs in OMAP5
ARM: OMAP5: Add the build support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: board-generic: Add device tree support
ARM: omap2+: board-generic: clean up the irq data from board file
ARM: OMAP5: Add SMP support
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: l3: Add l3 error handler support for omap5
ARM: OMAP5: gpmc: Update gpmc_init()
...
Conflicts:
Documentation/devicetree/bindings/arm/omap/omap.txt
arch/arm/mach-omap2/Makefile
drivers/clocksource/Kconfig
drivers/clocksource/Makefile
Diffstat (limited to 'arch/arm/mach-mvebu/irq-armada-370-xp.c')
-rw-r--r-- | arch/arm/mach-mvebu/irq-armada-370-xp.c | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c new file mode 100644 index 000000000000..5f5f9394b6b2 --- /dev/null +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -0,0 +1,133 @@ +/* + * Marvell Armada 370 and Armada XP SoC IRQ handling + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Ben Dooks <ben.dooks@codethink.co.uk> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/irqdomain.h> +#include <asm/mach/arch.h> +#include <asm/exception.h> + +/* Interrupt Controller Registers Map */ +#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) +#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) + +#define ARMADA_370_XP_INT_CONTROL (0x00) +#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) +#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) + +#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) + +static void __iomem *per_cpu_int_base; +static void __iomem *main_int_base; +static struct irq_domain *armada_370_xp_mpic_domain; + +static void armada_370_xp_irq_mask(struct irq_data *d) +{ + writel(irqd_to_hwirq(d), + per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); +} + +static void armada_370_xp_irq_unmask(struct irq_data *d) +{ + writel(irqd_to_hwirq(d), + per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); +} + +static struct irq_chip armada_370_xp_irq_chip = { + .name = "armada_370_xp_irq", + .irq_mask = armada_370_xp_irq_mask, + .irq_mask_ack = armada_370_xp_irq_mask, + .irq_unmask = armada_370_xp_irq_unmask, +}; + +static int armada_370_xp_mpic_irq_map(struct irq_domain *h, + unsigned int virq, irq_hw_number_t hw) +{ + armada_370_xp_irq_mask(irq_get_irq_data(virq)); + writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); + + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + + return 0; +} + +static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { + .map = armada_370_xp_mpic_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init armada_370_xp_mpic_of_init(struct device_node *node, + struct device_node *parent) +{ + u32 control; + + main_int_base = of_iomap(node, 0); + per_cpu_int_base = of_iomap(node, 1); + + BUG_ON(!main_int_base); + BUG_ON(!per_cpu_int_base); + + control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); + + armada_370_xp_mpic_domain = + irq_domain_add_linear(node, (control >> 2) & 0x3ff, + &armada_370_xp_mpic_irq_ops, NULL); + + if (!armada_370_xp_mpic_domain) + panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n"); + + irq_set_default_host(armada_370_xp_mpic_domain); + return 0; +} + +asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs + *regs) +{ + u32 irqstat, irqnr; + + do { + irqstat = readl_relaxed(per_cpu_int_base + + ARMADA_370_XP_CPU_INTACK_OFFS); + irqnr = irqstat & 0x3FF; + + if (irqnr < 1023) { + irqnr = + irq_find_mapping(armada_370_xp_mpic_domain, irqnr); + handle_IRQ(irqnr, regs); + continue; + } + + break; + } while (1); +} + +static const struct of_device_id mpic_of_match[] __initconst = { + {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init}, + {}, +}; + +void __init armada_370_xp_init_irq(void) +{ + of_irq_init(mpic_of_match); +} |