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authorPaul Walmsley <paul@pwsan.com>2009-06-20 05:08:27 +0400
committerpaul <paul@twilight.(none)>2009-06-20 05:09:31 +0400
commitd0ba3922ae241a87d22a1c3ffad72b96fe993c9a (patch)
tree3f23d60fbbf2ffceef44b01c8579db7be7d20025 /arch/arm/mach-omap2/clock34xx.c
parentc9812d042a21eb492a36cfabf9f41107f5ecee3d (diff)
downloadlinux-d0ba3922ae241a87d22a1c3ffad72b96fe993c9a.tar.xz
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 4bfa650bb34b..cf41ab55fa97 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -771,9 +771,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/* REVISIT: SRAM code doesn't support other M2 divisors yet */
WARN_ON(new_div != 1 && new_div != 2);
- /* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
- sp->actim_ctrlb, new_div, unlock_dll, c);
+ sp->actim_ctrlb, new_div, unlock_dll, c,
+ sp->mr);
return 0;
}