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authorPaul Walmsley <paul@pwsan.com>2010-12-22 05:56:17 +0300
committerPaul Walmsley <paul@pwsan.com>2010-12-22 05:56:17 +0300
commit81fbc5ef9b22df2e2198dd0c530719a263a8d1c5 (patch)
treee11b03021482b9ea8e0623a160eb86e03841b40d /arch/arm/mach-omap2/wd_timer.c
parent233cbe5b94096f95ba7bca2162d63275b0b90b5b (diff)
downloadlinux-81fbc5ef9b22df2e2198dd0c530719a263a8d1c5.tar.xz
OMAP2+: wd_timer: separate watchdog disable code from the rest of mach-omap2/devices.c
Split the wd_timer disable code out into its own file, mach-omap2/wd_timer.c; it belongs in its own file rather than cluttering up devices.c. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Charulatha Varadarajan <charu@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/wd_timer.c')
-rw-r--r--arch/arm/mach-omap2/wd_timer.c68
1 files changed, 68 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
new file mode 100644
index 000000000000..06c256d38988
--- /dev/null
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -0,0 +1,68 @@
+/*
+ * OMAP2+ MPU WD_TIMER-specific code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <plat/omap_hwmod.h>
+
+/*
+ * In order to avoid any assumptions from bootloader regarding WDT
+ * settings, WDT module is reset during init. This enables the watchdog
+ * timer. Hence it is required to disable the watchdog after the WDT reset
+ * during init. Otherwise the system would reboot as per the default
+ * watchdog timer registers settings.
+ */
+#define OMAP_WDT_WPS 0x34
+#define OMAP_WDT_SPR 0x48
+
+
+int omap2_wd_timer_disable(struct omap_hwmod *oh)
+{
+ void __iomem *base;
+ int ret;
+
+ if (!oh) {
+ pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
+ return -EINVAL;
+ }
+
+ base = omap_hwmod_get_mpu_rt_va(oh);
+ if (!base) {
+ pr_err("%s: Could not get the base address for %s\n",
+ oh->name, __func__);
+ return -EINVAL;
+ }
+
+ /* Enable the clocks before accessing the WDT registers */
+ ret = omap_hwmod_enable(oh);
+ if (ret) {
+ pr_err("%s: Could not enable clocks for %s\n",
+ oh->name, __func__);
+ return ret;
+ }
+
+ /* sequence required to disable watchdog */
+ __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+ while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+ cpu_relax();
+
+ __raw_writel(0x5555, base + OMAP_WDT_SPR);
+ while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+ cpu_relax();
+
+ ret = omap_hwmod_idle(oh);
+ if (ret)
+ pr_err("%s: Could not disable clocks for %s\n",
+ oh->name, __func__);
+
+ return ret;
+}
+