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authorArnd Bergmann <arnd@arndb.de>2022-04-04 23:37:04 +0300
committerArnd Bergmann <arnd@arndb.de>2022-05-07 23:56:17 +0300
commite6acc4062c02ee4a1a3ae961d073229f72e8f200 (patch)
tree88d3fad646d8929cbac27b64e787f53bb65282c7 /arch/arm/mach-pxa/regs-ost.h
parentc8a91428941b912d66e13a2719fe6ac670150d69 (diff)
downloadlinux-e6acc4062c02ee4a1a3ae961d073229f72e8f200.tar.xz
ARM: pxa: move mach/*.h to mach-pxa/
None of the headers are included from outside of the mach-pxa directory, so move them all in there. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-pxa/regs-ost.h')
-rw-r--r--arch/arm/mach-pxa/regs-ost.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/regs-ost.h b/arch/arm/mach-pxa/regs-ost.h
new file mode 100644
index 000000000000..c8001cfc8d6b
--- /dev/null
+++ b/arch/arm/mach-pxa/regs-ost.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_REGS_OST_H
+#define __ASM_MACH_REGS_OST_H
+
+#include "pxa-regs.h"
+
+/*
+ * OS Timer & Match Registers
+ */
+#define OST_PHYS 0x40A00000
+#define OST_LEN 0x00000020
+
+#define OSMR0 io_p2v(0x40A00000) /* */
+#define OSMR1 io_p2v(0x40A00004) /* */
+#define OSMR2 io_p2v(0x40A00008) /* */
+#define OSMR3 io_p2v(0x40A0000C) /* */
+#define OSMR4 io_p2v(0x40A00080) /* */
+#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
+#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
+#define OMCR4 io_p2v(0x40A000C0) /* */
+#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
+#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
+#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */
+
+#define OSSR_M3 (1 << 3) /* Match status channel 3 */
+#define OSSR_M2 (1 << 2) /* Match status channel 2 */
+#define OSSR_M1 (1 << 1) /* Match status channel 1 */
+#define OSSR_M0 (1 << 0) /* Match status channel 0 */
+
+#define OWER_WME (1 << 0) /* Watchdog Match Enable */
+
+#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
+#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
+#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
+#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
+
+#endif /* __ASM_MACH_REGS_OST_H */