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authorRussell King <rmk+kernel@armlinux.org.uk>2017-07-26 14:49:31 +0300
committerRussell King <rmk+kernel@armlinux.org.uk>2017-08-14 18:22:55 +0300
commit1abd35023763c099bf4ee7558faa261d5c9d5025 (patch)
tree9061bc04ffc6fe004f3405c0c28869a531fb4167 /arch/arm/mach-rockchip
parentce184a0dee92a0a333236a26478e304dca29a3df (diff)
downloadlinux-1abd35023763c099bf4ee7558faa261d5c9d5025.tar.xz
ARM: align .data section
Robert Jarzmik reports that his PXA25x system fails to boot with 4.12, failing at __flush_whole_cache in arch/arm/mm/proc-xscale.S:215: 0xc0019e20 <+0>: ldr r1, [pc, #788] 0xc0019e24 <+4>: ldr r0, [r1] <== here with r1 containing 0xc06f82cd, which is the address of "clean_addr". Examination of the System.map shows: c06f22c8 D user_pmd_table c06f22cc d __warned.19178 c06f22cd d clean_addr indicating that a .data.unlikely section has appeared just before the .data section from proc-xscale.S. According to objdump -h, it appears that our assembly files default their .data alignment to 2**0, which is bad news if the preceding .data section size is not power-of-2 aligned at link time. Add the appropriate .align directives to all assembly files in arch/arm that are missing them where we require an appropriate alignment. Reported-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mach-rockchip')
-rw-r--r--arch/arm/mach-rockchip/sleep.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S
index 2eec9a341f05..9927f06f52fe 100644
--- a/arch/arm/mach-rockchip/sleep.S
+++ b/arch/arm/mach-rockchip/sleep.S
@@ -23,7 +23,7 @@
* ddr to sram for system resumeing.
* so it is ".data section".
*/
-.align
+ .align 2
ENTRY(rockchip_slp_cpu_resume)
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off