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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-19 16:18:02 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 03:50:06 +0400
commitadf4b00ebf4e183f36d88d5a5a591c532fb0abe9 (patch)
tree55f37d9f98f18f8ae6af62b1d0c19ac900b0c5ef /arch/arm/mach-spear
parent8b5c18f05621394eb108d3fbc9bf98b05e8162db (diff)
downloadlinux-adf4b00ebf4e183f36d88d5a5a591c532fb0abe9.tar.xz
ARM: l2c: spear13xx: remove cache size override
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear')
-rw-r--r--arch/arm/mach-spear/spear13xx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index dcb300443b66..c9897ea38980 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -46,7 +46,7 @@ void __init spear13xx_l2x0_init(void)
*/
writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
- l2x0_init(VA_L2CC_BASE, 0x30a60001, 0xfe00ffff);
+ l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
}
/*