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| author | Dmitry Osipenko <digetx@gmail.com> | 2019-03-18 01:52:10 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-04-09 17:36:29 +0300 |
| commit | 78ee399f1632a00a92dcdb0ebba8cfe0081a3e5d (patch) | |
| tree | 1b76327a4ae5bb14eaec51454446b3ed9ab2d357 /arch/arm/mach-tegra/reset-handler.S | |
| parent | dae84be59d667089a7ad3d27a0662e6b71f13116 (diff) | |
| download | linux-78ee399f1632a00a92dcdb0ebba8cfe0081a3e5d.tar.xz | |
ARM: tegra: Add firmware calls required for suspend-resume on Tegra30
In order to suspend-resume CPU with Trusted Foundations firmware being
present on Tegra30, the LP1/LP2 boot vectors and CPU caches need to be
set up using the firmware calls and then suspend code shall avoid
re-disabling parts that were disabled by the firmware.
Tested-by: Robert Yang <decatf@gmail.com>
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset-handler.S')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 31fb53f9ce13..cd94d7c41fc0 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -20,6 +20,7 @@ #include <soc/tegra/flowctrl.h> #include <soc/tegra/fuse.h> +#include <asm/assembler.h> #include <asm/asm-offsets.h> #include <asm/cache.h> @@ -76,6 +77,7 @@ ENTRY(tegra_resume) orr r1, r1, #1 str r1, [r0] #endif + bl tegra_resume_trusted_foundations #ifdef CONFIG_CACHE_L2X0 /* L2 cache resume & re-enable */ @@ -88,6 +90,30 @@ end_ca9_scu_l2_resume: b cpu_resume ENDPROC(tegra_resume) + +/* + * tegra_resume_trusted_foundations + * + * Trusted Foundations firmware initialization. + * + * Doesn't return if firmware presents. + * Corrupted registers: r1, r2 + */ +ENTRY(tegra_resume_trusted_foundations) + /* Check whether Trusted Foundations firmware presents. */ + mov32 r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + ldr r1, =__tegra_cpu_reset_handler_data_offset + \ + RESET_DATA(TF_PRESENT) + ldr r1, [r2, r1] + cmp r1, #0 + reteq lr + + .arch_extension sec + /* First call after suspend wakes firmware. No arguments required. */ + smc #0 + + b cpu_resume +ENDPROC(tegra_resume_trusted_foundations) #endif .align L1_CACHE_SHIFT |