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| author | Linus Walleij <linus.walleij@linaro.org> | 2015-05-14 11:06:55 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-05-18 16:07:41 +0300 |
| commit | 583ecab9e36ec3077228cc4e303276856ee7519e (patch) | |
| tree | 63bacc6c6a4c43f5681c34bdd1230375f1b10fb6 /arch/arm/mach-ux500/cpu-db8500.c | |
| parent | c1424803f6467fbbf269a5dfa830d9c60ae32181 (diff) | |
| download | linux-583ecab9e36ec3077228cc4e303276856ee7519e.tar.xz | |
ARM: ux500: kill off L2CC static map
The l2x0 level 2 cache initialization used a static map
to get at the l2x0 registers. Get rid of this by getting
the register range from the device tree and just remap it
for the short time we need it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500/cpu-db8500.c')
| -rw-r--r-- | arch/arm/mach-ux500/cpu-db8500.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 3562b9aea767..fd0bc1978dbb 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -43,11 +43,6 @@ static struct prcmu_pdata db8500_prcmu_pdata = { .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, }; -/* U8500 and U9540 common io_desc */ -static struct map_desc u8500_common_io_desc[] __initdata = { - __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), -}; - /* U8500 IO map specific description */ static struct map_desc u8500_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), @@ -66,8 +61,6 @@ static void __init u8500_map_io(void) debug_ll_io_init(); ux500_map_io(); - iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc)); - if (cpu_is_ux540_family()) iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); else |