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authorNicolas Pitre <nicolas.pitre@linaro.org>2014-06-24 21:34:38 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-07-18 14:58:02 +0400
commit3592d7e002438980f9ce4a399f21ec94cbf071ea (patch)
tree494107a394fecad6df9f01c3c54a37882c6d5aef /arch/arm/mach-vexpress
parent3721924c81541d828d73d0e36dcbae8fd93f0885 (diff)
downloadlinux-3592d7e002438980f9ce4a399f21ec94cbf071ea.tar.xz
ARM: 8082/1: TC2: test the MCPM loopback during boot
This is not strictly needed on TC2 but still a good idea to exercise that code. Signed-off-by: nicolas Pitre <nico@linaro.org> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-vexpress')
-rw-r--r--arch/arm/mach-vexpress/tc2_pm.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index b743a0ae02ce..54a9fff77c7d 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -323,6 +323,21 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
" b cci_enable_port_for_self ");
}
+static void __init tc2_cache_off(void)
+{
+ pr_info("TC2: disabling cache during MCPM loopback test\n");
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+ /* disable L2 prefetching on the Cortex-A15 */
+ asm volatile(
+ "mcr p15, 1, %0, c15, c0, 3 \n\t"
+ "isb \n\t"
+ "dsb "
+ : : "r" (0x400) );
+ }
+ v7_exit_coherency_flush(all);
+ cci_disable_port_by_cpu(read_cpuid_mpidr());
+}
+
static int __init tc2_pm_init(void)
{
int ret, irq;
@@ -370,6 +385,8 @@ static int __init tc2_pm_init(void)
ret = mcpm_platform_register(&tc2_pm_power_ops);
if (!ret) {
mcpm_sync_init(tc2_pm_power_up_setup);
+ /* test if we can (re)enable the CCI on our own */
+ BUG_ON(mcpm_loopback(tc2_cache_off) != 0);
pr_info("TC2 power management initialized\n");
}
return ret;