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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2013-07-17 21:10:15 +0400
committerMichal Simek <michal.simek@xilinx.com>2013-07-26 16:14:41 +0400
commit3db9e86029349c2c84928b5a0f7c7cf324243b4f (patch)
treef1846c75949e77ff2770ab199649dfe775d60dfc /arch/arm/mach-zynq
parentb5f177ff305b3db63b5ea273e6471708790133f2 (diff)
downloadlinux-3db9e86029349c2c84928b5a0f7c7cf324243b4f.tar.xz
arm: zynq: slcr: Use read-modify-write for register writes
zynq_slcr_cpu_start/stop() ignored the current register state when writing to a register. Fixing this by implementing proper read-modify-write. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r--arch/arm/mach-zynq/slcr.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 44a4ab62e9a8..1836d5a34606 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -61,11 +61,11 @@ void zynq_slcr_system_reset(void)
*/
void zynq_slcr_cpu_start(int cpu)
{
- /* enable CPUn */
- writel(SLCR_A9_CPU_CLKSTOP << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
- /* enable CLK for CPUn */
- writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg &= ~(SLCR_A9_CPU_RST << cpu);
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**
@@ -74,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
*/
void zynq_slcr_cpu_stop(int cpu)
{
- /* stop CLK and reset CPUn */
- writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu,
- zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+ reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
+ writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
}
/**