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authorHyok S. Choi <hyok.choi@samsung.com>2006-09-28 16:46:16 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-28 23:15:46 +0400
commit0f45d7f36b766cb668cebfb5d4d2f67b4a8676ba (patch)
tree975c493fc13a2a078ef4d41374794faf1c5d1510 /arch/arm/mm/abort-lv4t.S
parent6cc7cbef948ea2660cc40d7aab090a479f7db6a2 (diff)
downloadlinux-0f45d7f36b766cb668cebfb5d4d2f67b4a8676ba.tar.xz
[ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a dummy abort handler which returns zero for the base restored Data Abort model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up for the base updated Data Abort model cores. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/abort-lv4t.S')
-rw-r--r--arch/arm/mm/abort-lv4t.S7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index db743e510214..9fb7b0e25ea1 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -19,11 +19,16 @@
*/
ENTRY(v4t_late_abort)
tst r3, #PSR_T_BIT @ check for thumb mode
+#ifdef CONFIG_CPU_CP15_MMU
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
+ bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
+#else
+ mov r0, #0 @ clear r0, r1 (no FSR/FAR)
+ mov r1, #0
+#endif
bne .data_thumb_abort
ldr r8, [r2] @ read arm instruction
- bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r8, #1 << 20 @ L = 1 -> write?
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24