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authorTorgue Alexandre <alexandre.torgue@st.com>2016-08-31 11:14:14 +0300
committerRussell King <rmk+kernel@armlinux.org.uk>2016-09-06 17:51:09 +0300
commit8e02676ffa6906a97de7f90772e9cdcb75ea6743 (patch)
tree56f3f1c122b4a9218eedd45d952211377b96a5a0 /arch/arm/mm/proc-v7m.S
parent6a8146f420be2e59cf511c5a046b762142ff201d (diff)
downloadlinux-8e02676ffa6906a97de7f90772e9cdcb75ea6743.tar.xz
ARM: 8610/1: V7M: Add dsb before jumping in handler mode
According to ARM AN321 (section 4.12): "If the vector table is in writable memory such as SRAM, either relocated by VTOR or a device dependent memory remapping mechanism, then architecturally a memory barrier instruction is required after the vector table entry is updated, and if the exception is to be activated immediately" Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7m.S')
-rw-r--r--arch/arm/mm/proc-v7m.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index e6786f007a59..f6d333f09bfe 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -132,6 +132,7 @@ __v7m_setup_cont:
badr r1, 1f
ldr r5, [r12, #11 * 4] @ read the SVC vector entry
str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
+ dsb
mov r6, lr @ save LR
ldr sp, =init_thread_union + THREAD_START_SP
cpsie i