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authorJernej Skrabec <jernej.skrabec@gmail.com>2021-11-20 10:34:47 +0300
committerMaxime Ripard <maxime@cerno.tech>2021-11-22 12:03:33 +0300
commit3047444def125d9e1fb788541e8dc18a7058a47a (patch)
tree0c4481821059f6d4e2d1df4565ad68b54ec7c6d2 /arch/arm64/boot/dts/allwinner
parent725bc607aa02d570c35c5f21c3eadc3342bf4e06 (diff)
downloadlinux-3047444def125d9e1fb788541e8dc18a7058a47a.tar.xz
arm64: dts: allwinner: a64: Add CEC clock to HDMI
Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211120073448.32480-2-jernej.skrabec@gmail.com
Diffstat (limited to 'arch/arm64/boot/dts/allwinner')
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 5ba379078500..741bd19fa8ec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1220,8 +1220,8 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu CLK_HDMI>;
- clock-names = "iahb", "isfr", "tmds";
+ <&ccu CLK_HDMI>, <&rtc 0>;
+ clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;