diff options
| author | Chanho Park <chanho61.park@samsung.com> | 2022-07-29 03:30:22 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-08-23 10:21:34 +0300 |
| commit | ac94f66521a5488eccdded4036b0ec039ceb87d5 (patch) | |
| tree | 7cd0aed408811f5d144e40988cf6191b18872150 /arch/arm64/boot/dts/exynos | |
| parent | 8f3fc0ed70b97e7544ec1a57c60fe6b2f2f778c3 (diff) | |
| download | linux-ac94f66521a5488eccdded4036b0ec039ceb87d5.tar.xz | |
arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks
respectively.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
[krzk: put nodes ordered by unit address]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/50f8145bca30cf5c900359d0b78c1c617090e021.1659054220.git.chanho61.park@samsung.com
Diffstat (limited to 'arch/arm64/boot/dts/exynos')
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 2013718532f3..5dc361734cfe 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -207,6 +207,34 @@ "dout_clkcmu_peric1_ip"; }; + cmu_fsys1: clock-controller@17040000 { + compatible = "samsung,exynosautov9-cmu-fsys1"; + reg = <0x17040000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, + <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, + <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; + clock-names = "oscclk", + "dout_clkcmu_fsys1_bus", + "gout_clkcmu_fsys1_mmc_card", + "dout_clkcmu_fsys1_usbdrd"; + }; + + cmu_fsys0: clock-controller@17700000 { + compatible = "samsung,exynosautov9-cmu-fsys0"; + reg = <0x17700000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; + clock-names = "oscclk", + "dout_clkcmu_fsys0_bus", + "dout_clkcmu_fsys0_pcie"; + }; + cmu_fsys2: clock-controller@17c00000 { compatible = "samsung,exynosautov9-cmu-fsys2"; reg = <0x17c00000 0x8000>; |