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| author | yong.liang <yong.liang@mediatek.com> | 2019-12-26 12:39:30 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2020-01-13 12:29:11 +0300 |
| commit | a845ad16212e3202589687713aae2d743e6b875c (patch) | |
| tree | db247879a9cbf892a4f5ba9e74f13938db978bcc /arch/arm64/boot/dts/mediatek/mt8183.dtsi | |
| parent | 1180beb08b9155ffdb982bfef0e3df280ab11ac5 (diff) | |
| download | linux-a845ad16212e3202589687713aae2d743e6b875c.tar.xz | |
arm64: dts: mt8183: add reset-cells in infracfg
Include mt8183-reset.h and add reset-cells in infracfg
in dtsi file
Signed-off-by: yong.liang <yong.liang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8183.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1ade9153e5c2..124f9d3e09f5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8183-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/reset-controller/mt8183-resets.h> #include "mt8183-pinfunc.h" / { @@ -227,6 +228,7 @@ compatible = "mediatek,mt8183-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pio: pinctrl@10005000 { |