diff options
| author | Nícolas F. R. A. Prado <nfraprado@collabora.com> | 2022-06-29 18:59:44 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2022-07-07 17:39:17 +0300 |
| commit | eb188a2aaa823849b8a5993fc0fd8a8c5e049c56 (patch) | |
| tree | a326d11e9b3e7cb0dbe432e8fac956a5123c2490 /arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | |
| parent | 23e0fff324b88855626077d7de7c83dde151707d (diff) | |
| download | linux-eb188a2aaa823849b8a5993fc0fd8a8c5e049c56.tar.xz | |
arm64: dts: mediatek: asurada: Add ChromeOS EC
Add support for the ChromeOS Embedded Controller present on the Asurada
platform. It is connected through the SPI1 bus and offers several
functionalities: base detection, PWM controller, I2C tunneling,
regulators, Type-C connector management, keyboard and Smart Battery
Metrics (SBS).
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220629155956.1138955-8-nfraprado@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 72dc974fe6fc..07405dea4d9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -353,6 +353,14 @@ "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = <PINMUX_GPIO204__FUNC_SCL0>, @@ -428,6 +436,74 @@ mediatek,pad-select = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + + #address-cells = <1>; + #size-cells = <0>; + + base_detection: cbas { + compatible = "google,cros-cbas"; + }; + + cros_ec_pwm: pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + + status = "disabled"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt6360_ldo3_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + mt6360_ldo5_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; }; &spi5 { @@ -442,3 +518,6 @@ &uart0 { status = "okay"; }; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> |