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author | Thierry Reding <treding@nvidia.com> | 2022-11-17 11:38:34 +0300 |
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committer | Thierry Reding <treding@nvidia.com> | 2023-01-17 15:55:04 +0300 |
commit | 2838cfddbc1c4e12dacf8219efb481ab11c114a4 (patch) | |
tree | fe3821dba66112b6829d4a6140b750b558bc434b /arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | |
parent | c71e18973be1c0ce65dcb45bfd0e1e755bab6d26 (diff) | |
download | linux-2838cfddbc1c4e12dacf8219efb481ab11c114a4.tar.xz |
arm64: tegra: Bump #address-cells and #size-cells
The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
the IP blocks on that bus. However, most of these devices can do DMA to
a larger address space, so translation of DMA addresses needs to happen
in a 64-bit address space.
Partially this was already done by the memory controller increasing that
address space by setting #address-cells and #size-cells to 2, but a full
DMA address translation would still cause truncation when traversing to
the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the
top-level bus and adjusting all "reg" and "ranges" properties of its
children.
While at it, also move the PCI and GPU nodes back under the top-level
bus where they belong. The were put outside of it to work around this
same problem.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi')
0 files changed, 0 insertions, 0 deletions