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authorJon Hunter <jonathanh@nvidia.com>2023-03-06 18:01:57 +0300
committerThierry Reding <treding@nvidia.com>2023-04-03 18:01:20 +0300
commit8e0ae0fb4b91655bcdca2a4d7d16ebb81fc5d786 (patch)
tree47e04d33c2943800d1b5d6bd35254ac0bc48d6ca /arch/arm64/boot/dts/nvidia
parent71de0a054d0ee1f9d0b13401330069cdb8f3e50a (diff)
downloadlinux-8e0ae0fb4b91655bcdca2a4d7d16ebb81fc5d786.tar.xz
arm64: tegra: Add DSU PMUs for Tegra234
Populate the DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) devices for Tegra234 which has one DSU PMU per CPU cluster. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234.dtsi18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index b9caf6d2d975..01504ede6334 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -3400,6 +3400,24 @@
};
};
+ dsu-pmu0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>;
+ };
+
+ dsu-pmu1 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>;
+ };
+
+ dsu-pmu2 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>;
+ };
+
pmu {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;