diff options
| author | Bjorn Andersson <quic_bjorande@quicinc.com> | 2023-05-18 02:52:17 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-23 06:00:24 +0300 |
| commit | ef026e592baa01dd7402511e5ced90f4b3ac3d2c (patch) | |
| tree | 0a8a8acab097fa49f58ab7d93a7e640ec7e054ab /arch/arm64/boot/dts/qcom/sc8280xp.dtsi | |
| parent | 42b08375498e74f094425fad10d10c338fd29858 (diff) | |
| download | linux-ef026e592baa01dd7402511e5ced90f4b3ac3d2c.tar.xz | |
arm64: dts: qcom: sc8280xp: Add SDC2 and enable on CRD
The CRD has Micro SD slot, introduce the necessary DeviceTree nodes for
enabling this.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517235217.1728548-1-quic_bjorande@quicinc.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc8280xp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 84ef3bd6d49a..4f64adadcdb5 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2845,6 +2845,49 @@ }; }; + sdc2: mmc@8804000 { + compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4e0 0x0>; + power-domains = <&rpmhpd SC8280XP_CX>; + operating-points-v2 = <&sdc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; + }; + }; + }; + usb_0_qmpphy: phy@88eb000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x088eb000 0 0x4000>; |