diff options
| author | Douglas Anderson <dianders@chromium.org> | 2023-03-23 20:30:18 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-04-07 20:54:09 +0300 |
| commit | 9f5cdeb7031062a36e135ebb88bd99c03f32e5ee (patch) | |
| tree | 3aca97738a6ae988f6c536fbb2f7043c2342ab16 /arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | |
| parent | 5f89df31096d67c244d8f36502f651ce701ddcde (diff) | |
| download | linux-9f5cdeb7031062a36e135ebb88bd99c03f32e5ee.tar.xz | |
arm64: dts: qcom: sdm845: Fix cheza qspi pin config
Cheza's SPI flash hookups (qspi) are exactly the same as trogdor's.
Apply the same solution that's described in the patch ("arm64: dts:
qcom: sc7180: Fix trogdor qspi pin config")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.14.I82951106ab8170f973a4c1c7d9b034655bbe2f60@changeid
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 34 |
1 files changed, 27 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index e1bab53642ab..d05c511718df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -317,8 +317,9 @@ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; flash@0 { compatible = "jedec,spi-nor"; @@ -993,16 +994,19 @@ ap_ts_i2c: &i2c14 { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { - bias-disable; + bias-disable; /* Rely on Cr50 internal pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-disable; /* Rely on Cr50 internal pulldown */ +}; + +&qspi_data1 { + bias-pull-down; }; &qup_i2c3_default { @@ -1231,6 +1235,22 @@ ap_ts_i2c: &i2c14 { output-high; }; + qspi_sleep: qspi-sleep-state { + pins = "gpio90", "gpio91", "gpio92", "gpio95"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; + sdc2_clk: sdc2-clk-state { pins = "sdc2_clk"; bias-disable; |