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| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2019-01-31 14:34:10 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-02-08 13:49:07 +0300 |
| commit | 231d8908a66fa98f09553d31ad8cd5f382b29959 (patch) | |
| tree | fdba5f1e417b3fa2585cff5abc480d267c4f29e8 /arch/arm64/boot/dts/renesas/r8a774c0.dtsi | |
| parent | dd7188eb4ed128dccc16b1d7dc1d639ddbd8882a (diff) | |
| download | linux-231d8908a66fa98f09553d31ad8cd5f382b29959.tar.xz | |
arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
This patch defines OOP tables for all CPUs, similarly to
what done by Takeshi Kihara and Yoshihiro Kaneko for the
R8A77990.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774c0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f2e390f7f1d5..71ff43e3bb41 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -44,6 +44,27 @@ clock-frequency = <0>; }; + cluster1_opp: opp_table10 { + compatible = "operating-points-v2"; + opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -55,6 +76,8 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@1 { @@ -64,6 +87,8 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA53: cache-controller-0 { |