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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-07 21:03:25 +0300 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-10 12:27:02 +0300 |
commit | b4dc3b4b1a65fec829ee8704c7647c06a8038108 (patch) | |
tree | 1bf0590094bf0a4be86c768da76024b33839ee56 /arch/arm64/boot/dts/renesas/r8a7796.dtsi | |
parent | a681e6d63285b879bb9bab0bd79e2021e6dcbda1 (diff) | |
download | linux-b4dc3b4b1a65fec829ee8704c7647c06a8038108.tar.xz |
arm64: dts: r8a7796: Add Cortex-A53 CPU cores
This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of
6 cores (2 x Cortex-A57 + 4 x Cortex-A53).
Based on a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 46 |
1 files changed, 41 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index b951f5ffe9e0..b32a180009dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -55,6 +55,42 @@ enable-method = "psci"; }; + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A7796_PD_CA57_SCU>; @@ -115,7 +151,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -124,13 +160,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; }; wdt0: watchdog@e6020000 { |