diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-19 18:38:40 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-30 16:07:25 +0300 |
| commit | 84365481610550aa43ca435d38af7b86c83a21de (patch) | |
| tree | 9f54a8ef713aeff70a2be3eb77ab2d8ffbf9305b /arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts | |
| parent | c532a55c9b4b1740427b9b8173ac756b5acbee1b (diff) | |
| download | linux-84365481610550aa43ca435d38af7b86c83a21de.tar.xz | |
arm64: dts: renesas: Add support for M3ULCB with R-Car M3e-2G
Add support for the Renesas R-Car Starter Kit Pro equipped with an R-Car
M3e-2G SiP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/c566dfa5f07605a467f8705c3a2f637ea445b1ff.1626708063.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts new file mode 100644 index 000000000000..8f215a0b771b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) with R-Car M3e-2G + * + * Copyright (C) 2021 Glider bv + * + * Based on r8a77961-ulcb.dts + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779m3.dtsi" +#include "ulcb.dtsi" + +/ { + model = "Renesas M3ULCB board based on r8a779m3"; + compatible = "renesas,m3ulcb", "renesas,r8a779m3", "renesas,r8a77961"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&versaclock5 3>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; |