diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-03 22:56:00 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 12:06:13 +0300 |
| commit | 5a8aa63c9bca800e6049d90422abe5404227a703 (patch) | |
| tree | 5592306ab15fae55b58a2ded8d21e0910c83ed06 /arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | |
| parent | 68f8eb19c18a377181622e58c1fd2ca0f5c0d15d (diff) | |
| download | linux-5a8aa63c9bca800e6049d90422abe5404227a703.tar.xz | |
arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board
SCIF2 interface is available on PMOD1 connector (CN7) on carrier board,
This patch adds pinmux and scif2 node to carrier board dtsi file.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103195600.23964-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 2863e487a640..4c32f068a1f0 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -21,9 +21,13 @@ * */ +/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + / { aliases { serial0 = &scif0; + serial1 = &scif2; i2c0 = &i2c0; i2c1 = &i2c1; i2c3 = &i2c3; @@ -208,6 +212,13 @@ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ }; + scif2_pins: scif2 { + pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */ + <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */ + <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; @@ -277,6 +288,23 @@ status = "okay"; }; +/* + * To enable SCIF2 (SER0) on PMOD1 (CN7) + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if PMOD1_SER0 +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; |