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authorSuman Anna <s-anna@ti.com>2024-02-15 13:30:34 +0300
committerVignesh Raghavendra <vigneshr@ti.com>2024-02-19 11:12:01 +0300
commitd4e8c8ad5d14ad51ed8813442d81c43019fd669d (patch)
treed7e4f887923bf1f57ed7c9db852148fbec3b58d0 /arch/arm64/boot/dts/ti
parent5f0e6ce354f61092182b79d177585bd7310f12a2 (diff)
downloadlinux-d4e8c8ad5d14ad51ed8813442d81c43019fd669d.tar.xz
arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes
The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be derived from either of the IP instance's ICSSG_IEP_GCLK or from another internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG instances. The IEP clock is currently configured to be derived indirectly from the ICSSG_ICLK running at 250 MHz. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Link: https://lore.kernel.org/r/20240215103036.2825096-2-danishanwar@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am64-main.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 3c6e9af1b059..6f9aa5e02138 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1235,6 +1235,18 @@
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1376,6 +1388,18 @@
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;