diff options
| author | Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> | 2022-04-22 05:39:44 +0300 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> | 2022-05-10 05:18:01 +0300 |
| commit | 340657b179165410ec6ca30db6e6d7fc5c366ca1 (patch) | |
| tree | 5f9af5f7e5cc826a9b12bb7a6072e0aae4d0bcf7 /arch/arm64/boot/dts/toshiba | |
| parent | 27b754902dab93d1c3bde94e97983ca0fe81f253 (diff) | |
| download | linux-340657b179165410ec6ca30db6e6d7fc5c366ca1.tar.xz | |
arm64: dts: visconti: Update the clock providers for SPI
Remove fixed clock and source common clock for SPI.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Link: https://lore.kernel.org/r/20220510015229.139818-5-nobuhiro1.iwamatsu@toshiba.co.jp/
Diffstat (limited to 'arch/arm64/boot/dts/toshiba')
| -rw-r--r-- | arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 21 |
2 files changed, 14 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index adfe8406c24c..0c8321022a73 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -25,8 +25,6 @@ &spi0 { status = "okay"; - clocks = <&clk300mhz>, <&clk150mhz>; - clock-names = "sspclk", "apb_pclk"; mmc-slot@0 { compatible = "mmc-spi-slot"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 6050796a1678..196cda7b5d90 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -143,13 +143,6 @@ clock-output-names = "clk125mhz"; }; - clk150mhz: clk150mhz { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - clock-output-names = "clk150mhz"; - }; - clk300mhz: clk300mhz { compatible = "fixed-clock"; clock-frequency = <300000000>; @@ -395,6 +388,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -407,6 +402,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -419,6 +416,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI2>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -431,6 +430,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI3>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -443,6 +444,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI4>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -455,6 +458,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI5>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -467,6 +472,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI6>; + clock-names = "apb_pclk"; status = "disabled"; }; |