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authorVaralaxmi Bingi <varalaxmi.bingi@amd.com>2023-06-08 15:36:10 +0300
committerMichal Simek <michal.simek@amd.com>2023-07-10 13:05:41 +0300
commit3175b52251f230713fd54686a76cf2f1365e94de (patch)
tree9e099cc79531864221109cd6522ddf70f43bdb0d /arch/arm64/boot/dts
parentee6c637f383fc6d1e1c358c829bd762240ccf259 (diff)
downloadlinux-3175b52251f230713fd54686a76cf2f1365e94de.tar.xz
arm64: zynqmp: Setting default i2c clock frequency to 400kHz
Setting default i2c clock frequency for ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3034ec006c8b11e025904d4cc2524255523636f6.1686227766.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 394db49ac6cb..675b88190845 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -648,6 +648,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -659,6 +660,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;