diff options
author | Olof Johansson <olof@lixom.net> | 2020-09-26 20:15:11 +0300 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2020-09-26 20:15:12 +0300 |
commit | 5310d705a934fdb6565824ab91a7be07c290ef47 (patch) | |
tree | a061533aa8ba013666a653056e5a16d7f86d7be4 /arch/arm64/boot | |
parent | 12f0f6f654d82bb4583956a5efcdf5aa6bcf3d58 (diff) | |
parent | 66db854b1f62dbee48ec7373f149fa30e4b3dd4e (diff) | |
download | linux-5310d705a934fdb6565824ab91a7be07c290ef47.tar.xz |
Merge tag 'ti-k3-dt-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt
Device tree updates towards 5.10-rc1 for TI K3 platform.
* tag 'ti-k3-dt-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (23 commits)
arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances
arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
arm64: dts: ti: k3-*: Fix up node_name_chars_strict warnings
arm64: dts: ti: k3-am65-wakeup: Use generic temperature-sensor for node name
arm64: dts: ti: k3-am65-base-board Use generic camera for node name instead of ov5640
arm64: dts: ti: k3-*: Use generic pinctrl for node names
arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names
arm64: dts: ti: k3-am65*: Use generic gpio for node names
arm64: dts: ti: k3-am65-main: Use lower case hexadecimal
arm64: dts: ti: k3-j721e: Use lower case hexadecimal
arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSP
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPs
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts file
arm64: dts: ti: k3-j721e-main: Add crypto accelerator node
...
Link: https://lore.kernel.org/r/20200922134722.2y5kqxu4lghbwp5u@akan
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 6 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65.dtsi | 6 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 18 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi | 12 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 191 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 301 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 155 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e.dtsi | 11 |
11 files changed, 608 insertions, 152 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 24ef18fe77df..533525229a8d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -112,7 +112,29 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; }; - main_pmx0: pinmux@11c000 { + crypto: crypto@4e00000 { + compatible = "ti,am654-sa2ul"; + reg = <0x0 0x4e00000 0x0 0x1200>; + power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; + status = "okay"; + + dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, + <&main_udmap 0x4001>; + dma-names = "tx", "rx1", "rx2"; + dma-coherent; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x0 0x4e10000 0x0 0x7d>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 136 1>; + }; + }; + + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; reg = <0x0 0x11c000 0x0 0x2e4>; #pinctrl-cells = <1>; @@ -120,7 +142,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - main_pmx1: pinmux@11c2e8 { + main_pmx1: pinctrl@11c2e8 { compatible = "pinctrl-single"; reg = <0x0 0x11c2e8 0x0 0x24>; #pinctrl-cells = <1>; @@ -283,7 +305,7 @@ no-1-8-v; }; - scm_conf: scm_conf@100000 { + scm_conf: scm-conf@100000 { compatible = "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; #address-cells = <1>; @@ -305,12 +327,12 @@ reg = <0x00000210 0x4>; }; - serdes0_clk: serdes_clk@4080 { + serdes0_clk: clock@4080 { compatible = "syscon"; reg = <0x00004080 0x4>; }; - serdes1_clk: serdes_clk@4090 { + serdes1_clk: clock@4090 { compatible = "syscon"; reg = <0x00004090 0x4>; }; @@ -322,12 +344,12 @@ <0x4090 0x3>; /* SERDES1 lane select */ }; - dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 { + dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { compatible = "syscon"; - reg = <0x0000041E0 0x14>; + reg = <0x0000041e0 0x14>; }; - ehrpwm_tbclk: syscon@4140 { + ehrpwm_tbclk: clock@4140 { compatible = "ti,am654-ehrpwm-tbclk", "syscon"; reg = <0x4140 0x18>; #clock-cells = <1>; @@ -423,7 +445,7 @@ ti,interrupt-ranges = <0 392 32>; }; - main_navss { + main-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -639,7 +661,7 @@ }; }; - main_gpio0: main_gpio0@600000 { + main_gpio0: gpio@600000 { compatible = "ti,am654-gpio", "ti,keystone-gpio"; reg = <0x0 0x600000 0x0 0x100>; gpio-controller; @@ -654,7 +676,7 @@ clock-names = "gpio"; }; - main_gpio1: main_gpio1@601000 { + main_gpio1: gpio@601000 { compatible = "ti,am654-gpio", "ti,keystone-gpio"; reg = <0x0 0x601000 0x0 0x100>; gpio-controller; @@ -682,7 +704,7 @@ ti,syscon-pcie-mode = <&pcie0_mode>; bus-range = <0x0 0xff>; num-viewport = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; msi-map = <0x0 &gic_its 0x0 0x10000>; @@ -696,7 +718,7 @@ ti,syscon-pcie-mode = <&pcie0_mode>; num-ib-windows = <16>; num-ob-windows = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; }; @@ -714,7 +736,7 @@ ti,syscon-pcie-mode = <&pcie1_mode>; bus-range = <0x0 0xff>; num-viewport = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; msi-map = <0x0 &gic_its 0x10000 0x10000>; @@ -728,7 +750,7 @@ ti,syscon-pcie-mode = <&pcie1_mode>; num-ib-windows = <16>; num-ob-windows = <16>; - max-link-speed = <3>; + max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 51ca4b4d4c21..29aaf8dca6f6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -6,7 +6,7 @@ */ &cbass_mcu { - mcu_conf: scm_conf@40f00000 { + mcu_conf: scm-conf@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x40f00000 0x0 0x20000>; #address-cells = <1>; @@ -116,7 +116,7 @@ }; }; - mcu_navss { + mcu-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index a1ffe88d9664..ed42f13e7663 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -39,7 +39,7 @@ reg = <0x43000014 0x4>; }; - wkup_pmx0: pinmux@4301c000 { + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; reg = <0x4301c000 0x118>; #pinctrl-cells = <1>; @@ -80,7 +80,7 @@ ti,interrupt-ranges = <0 712 16>; }; - wkup_gpio0: wkup_gpio0@42110000 { + wkup_gpio0: gpio@42110000 { compatible = "ti,am654-gpio", "ti,keystone-gpio"; reg = <0x42110000 0x100>; gpio-controller; @@ -95,7 +95,7 @@ clock-names = "gpio"; }; - wkup_vtm0: thermal@42050000 { + wkup_vtm0: temperature-sensor@42050000 { compatible = "ti,am654-vtm"; reg = <0x42050000 0x25c>; power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 27c0406b10ba..d84c0bc05023 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -61,7 +61,7 @@ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; - cbass_main: interconnect@100000 { + cbass_main: bus@100000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -88,7 +88,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; - cbass_mcu: interconnect@28380000 { + cbass_mcu: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -106,7 +106,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ - cbass_wakeup: interconnect@42040000 { + cbass_wakeup: bus@42040000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index b8a8a0fcb8af..d12dd89f3405 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -29,7 +29,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - secure_ddr: secure_ddr@9e800000 { + secure_ddr: secure-ddr@9e800000 { reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ alignment = <0x1000>; no-map; @@ -70,14 +70,14 @@ >; }; - push_button_pins_default: push_button__pins_default { + push_button_pins_default: push-button-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ @@ -93,13 +93,13 @@ >; }; - wkup_pca554_default: wkup_pca554_default { + wkup_pca554_default: wkup-pca554-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ >; }; - mcu_cpsw_pins_default: mcu_cpsw_pins_default { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ @@ -116,7 +116,7 @@ >; }; - mcu_mdio_pins_default: mcu_mdio1_pins_default { + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ @@ -167,7 +167,7 @@ >; }; - main_mmc1_pins_default: main_mmc1_pins_default { + main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -180,7 +180,7 @@ >; }; - usb1_pins_default: usb1_pins_default { + usb1_pins_default: usb1-pins-default { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; @@ -257,7 +257,7 @@ pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; - ov5640@3c { + ov5640: camera@3c { compatible = "ovti,ov5640"; reg = <0x3c>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi index cdc3d40c3f60..9021c738056b 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi @@ -2,13 +2,13 @@ #include <dt-bindings/thermal/thermal.h> -mpu0_thermal: mpu0_thermal { +mpu0_thermal: mpu0-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <500>; /* milliseconds */ thermal-sensors = <&wkup_vtm0 0>; trips { - mpu0_crit: mpu0_crit { + mpu0_crit: mpu0-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; @@ -16,13 +16,13 @@ mpu0_thermal: mpu0_thermal { }; }; -mpu1_thermal: mpu1_thermal { +mpu1_thermal: mpu1-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <500>; /* milliseconds */ thermal-sensors = <&wkup_vtm0 1>; trips { - mpu1_crit: mpu1_crit { + mpu1_crit: mpu1-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; @@ -30,13 +30,13 @@ mpu1_thermal: mpu1_thermal { }; }; -mcu_thermal: mcu_thermal { +mcu_thermal: mcu-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <500>; /* milliseconds */ thermal-sensors = <&wkup_vtm0 2>; trips { - mcu_crit: mcu_crit { + mcu_crit: mcu-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e8fc01d97ada..f35a5d5b1cd8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -86,13 +86,13 @@ }; &main_pmx0 { - sw10_button_pins_default: sw10_button_pins_default { + sw10_button_pins_default: sw10-button-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ >; }; - main_mmc1_pins_default: main_mmc1_pins_default { + main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -106,14 +106,14 @@ >; }; - main_usbss0_pins_default: main_usbss0_pins_default { + main_usbss0_pins_default: main-usbss0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main_usbss1_pins_default { + main_usbss1_pins_default: main-usbss1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; @@ -153,7 +153,7 @@ >; }; - mcasp10_pins_default: mcasp10_pins_default { + mcasp10_pins_default: mcasp10-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ @@ -167,7 +167,7 @@ >; }; - audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default { + audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; @@ -175,7 +175,7 @@ }; &wkup_pmx0 { - sw11_button_pins_default: sw11_button_pins_default { + sw11_button_pins_default: sw11-button-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ >; @@ -194,7 +194,7 @@ >; }; - mcu_cpsw_pins_default: mcu_cpsw_pins_default { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -211,7 +211,7 @@ >; }; - mcu_mdio_pins_default: mcu_mdio1_pins_default { + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ @@ -286,99 +286,6 @@ status = "disabled"; }; -&mailbox0_cluster0 { - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &main_sdhci0 { /* eMMC */ non-removable; @@ -651,3 +558,83 @@ status = "okay"; }; + +&serdes0 { + serdes0_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&serdes2 { + serdes2_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie2_rc { + reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + +&pcie1_ep { + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie2_ep { + phys = <&serdes2_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; + +&pcie3_rc { + status = "disabled"; +}; + +&pcie3_ep { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 12ceea9b3c9a..824ccd7a414d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,7 +28,39 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - serdes_ln_ctrl: serdes-ln-ctrl@4080 { + pcie0_ctrl: syscon@4070 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004070 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4070 0x4070 0x4>; + }; + + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + + pcie2_ctrl: syscon@4078 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004078 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4078 0x4078 0x4>; + }; + + pcie3_ctrl: syscon@407c { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x0000407c 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x407c 0x407c 0x4>; + }; + + serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; #mux-control-cells = <1>; @@ -86,7 +118,7 @@ ti,interrupt-ranges = <8 392 56>; }; - main_navss { + main-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -304,7 +336,30 @@ }; }; - main_pmx0: pinmux@11c000 { + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x0 0x4e00000 0x0 0x1200>; + power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; + + status = "okay"; + + dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, + <&main_udmap 0x4001>; + dma-names = "tx", "rx1", "rx2"; + dma-coherent; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x0 0x4e10000 0x0 0x7d>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 264 1>; + }; + }; + + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x0 0x11c000 0x0 0x2b4>; @@ -553,6 +608,204 @@ }; }; + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie0_ep: pcie-ep@2900000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie2_rc: pcie@2920000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x20000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie2_ep: pcie-ep@2920000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02920000 0x00 0x1000>, + <0x00 0x02927000 0x00 0x400>, + <0x00 0x0e000000 0x00 0x00800000>, + <0x44 0x00000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 241 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + }; + + pcie3_rc: pcie@2930000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x30000 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie3_ep: pcie-ep@2930000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02930000 0x00 0x1000>, + <0x00 0x02937000 0x00 0x400>, + <0x00 0x0e800000 0x00 0x00800000>, + <0x44 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 242 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; + dma-coherent; + #address-cells = <2>; + #size-cells = <2>; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -865,7 +1118,7 @@ no-1-8-v; }; - usbss0: cdns_usb@4104000 { + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; dma-coherent; @@ -895,7 +1148,7 @@ }; }; - usbss1: cdns_usb@4114000 { + usbss1: cdns-usb@4114000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4114000 0x00 0x100>; dma-coherent; @@ -1326,4 +1579,42 @@ assigned-clocks = <&k3_clks 253 1>; assigned-clock-parents = <&k3_clks 253 5>; }; + + c66_0: dsp@4d80800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x80800000 0x00 0x00048000>, + <0x4d 0x80e00000 0x00 0x00008000>, + <0x4d 0x80f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <142>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 142 1>; + firmware-name = "j7-c66_0-fw"; + }; + + c66_1: dsp@4d81800000 { + compatible = "ti,j721e-c66-dsp"; + reg = <0x4d 0x81800000 0x00 0x00048000>, + <0x4d 0x81e00000 0x00 0x00008000>, + <0x4d 0x81f00000 0x00 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <143>; + ti,sci-proc-ids = <0x04 0xff>; + resets = <&k3_reset 143 1>; + firmware-name = "j7-c66_1-fw"; + }; + + c71_0: dsp@64800000 { + compatible = "ti,j721e-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <15>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 15 1>; + firmware-name = "j7-c71_0-fw"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index c4a48e8d420a..e581cb1d87ee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -53,7 +53,7 @@ reg = <0x0 0x43000014 0x0 0x4>; }; - wkup_pmx0: pinmux@4301c000 { + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x178>; @@ -249,7 +249,7 @@ }; }; - mcu_navss { + mcu-navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 8fa3361e5e45..5dc3ba739131 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -25,11 +25,53 @@ alignment = <0x1000>; no-map; }; + + c66_1_dma_memory_region: c66-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: c66-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c66_0_dma_memory_region: c66-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: c66-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup_i2c0_pins_default { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ @@ -72,3 +114,114 @@ #size-cells = <1>; }; }; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&c66_0 { + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index d035b61e0e16..cc483f7344af 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -120,21 +120,24 @@ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; - cbass_main: interconnect@100000 { + cbass_main: bus@100000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ @@ -155,7 +158,7 @@ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - cbass_mcu_wakeup: interconnect@28380000 { + cbass_mcu_wakeup: bus@28380000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; |