diff options
author | Arnd Bergmann <arnd@arndb.de> | 2022-08-02 17:09:12 +0300 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2022-08-02 17:09:13 +0300 |
commit | 0d98fbcf72f11b6a6fadcec16d4c7f317bf417ae (patch) | |
tree | 6018107f42bed383f7416e9d7309a92c737feb34 /arch/arm64/boot | |
parent | 87df0cecc269317def877ed05966781e4389d122 (diff) | |
parent | b3cbbb58632fa6f9cebf3f5c3ba210f11a3bdeb8 (diff) | |
download | linux-0d98fbcf72f11b6a6fadcec16d4c7f317bf417ae.tar.xz |
Merge tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late
SoCFPGA dts updates for v5.20, part 2
- Update EMAC AXI settings for Cyclone5
* tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: add EMAC AXI settings for Cyclone5
arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
arm64: dts: Add support for Stratix 10 Software Virtual Platform
dt-bindings: altera: document Stratix 10 SWVP compatibles
arm64: dts: altera: adjust whitespace around '='
arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
dt-bindings: altera: Add Chameleon v3 board
ARM: dts: socfpga: Add Google Chameleon v3 devicetree
ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi
Link: https://lore.kernel.org/r/20220728223237.3184243-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/altera/Makefile | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 58 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 10 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 10 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts | 117 | ||||
-rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 14 |
6 files changed, 163 insertions, 49 deletions
diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 4db83fbeb115..1bf0c472f6b4 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb + socfpga_stratix10_socdk_nand.dtb \ + socfpga_stratix10_swvp.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index aa2bba75265f..14c220d87807 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -97,6 +97,34 @@ <0x0 0xfffc6000 0x0 0x2000>; }; + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -119,34 +147,6 @@ #clock-cells = <1>; }; - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; @@ -594,7 +594,7 @@ }; qspi: spi@ff8d2000 { - compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 5159cd5771dc..48424e459f12 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -52,12 +52,6 @@ }; soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - eccmgr { sdmmca-ecc@ff8c8c00 { compatible = "altr,socfpga-s10-sdmmc-ecc", @@ -113,6 +107,10 @@ bus-width = <4>; }; +&osc1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 0ab676c639a1..847a7c01f5af 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -52,12 +52,6 @@ }; soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - eccmgr { sdmmca-ecc@ff8c8c00 { compatible = "altr,socfpga-s10-sdmmc-ecc", @@ -126,6 +120,10 @@ }; }; +&osc1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts new file mode 100644 index 000000000000..a8db58573954 --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SOCFPGA Stratix 10 SWVP"; + compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + linux,initrd-start = <0x10000000>; + linux,initrd-end = <0x125c8324>; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&cpu0 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu1 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu2 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu3 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; + snps,max-mtu = <0x0>; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&mmc { + status = "okay"; + altr,dw-mshc-ciu-div = <0x3>; + altr,dw-mshc-sdr-timing = <0x0 0x3>; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&usb1 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&rst { + altr,modrst-offset = <0x20>; +}; + +&sysmgr { + reg = <0xffd12000 0x1000>; + interrupts = <0x0 0x10 0x4>; + cpu1-start-addr = <0xffd06230>; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index caccb0334ada..7bbec8aafa62 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -581,7 +581,7 @@ sdramedac { compatible = "altr,sdram-edac-s10"; altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; }; ocram-ecc@ff8cc000 { @@ -589,7 +589,7 @@ "altr,socfpga-a10-ocram-ecc"; reg = <0xff8cc000 0x100>; altr,ecc-parent = <&ocram>; - interrupts = <1 4>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; usb0-ecc@ff8c4000 { @@ -597,7 +597,7 @@ "altr,socfpga-usb-ecc"; reg = <0xff8c4000 0x100>; altr,ecc-parent = <&usb0>; - interrupts = <2 4>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; emac0-rx-ecc@ff8c0000 { @@ -605,7 +605,7 @@ "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0000 0x100>; altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; }; emac0-tx-ecc@ff8c0400 { @@ -613,7 +613,7 @@ "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0400 0x100>; altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; sdmmca-ecc@ff8c8c00 { @@ -621,8 +621,8 @@ "altr,socfpga-sdmmc-ecc"; reg = <0xff8c8c00 0x100>; altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; }; }; |