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| author | Rafał Miłecki <rafal@milecki.pl> | 2024-01-08 11:52:28 +0300 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-02-12 15:36:57 +0300 |
| commit | b616b403cbffc6842767c4eb9ee7b11b20940098 (patch) | |
| tree | a8e0c126b9db4d1b2d67f7793f6fde96032010f2 /arch/arm64/boot | |
| parent | 6c1d134a103f68ca4d6bd2a509262fba5c032725 (diff) | |
| download | linux-b616b403cbffc6842767c4eb9ee7b11b20940098.tar.xz | |
arm64: dts: mediatek: mt7988: add clock controllers
Add bindings of on-SoC clocks.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20240108085228.4727-4-zajec5@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 5a778188ac21..bba97de4fb44 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -78,12 +78,51 @@ #interrupt-cells = <3>; }; - watchdog@1001c000 { + clock-controller@10001000 { + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { compatible = "mediatek,mt7988-wdt"; reg = <0 0x1001c000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + clock-controller@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog 16>; + #clock-cells = <1>; + }; + + clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; timer { |