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authorWill Deacon <will.deacon@arm.com>2017-03-10 23:32:24 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2017-03-20 19:17:02 +0300
commitdda288d7e4f605632dc6e19c69063f1725056208 (patch)
tree72ee2d87ea23475afc08611168ff64257b9dab84 /arch/arm64/include/asm/cache.h
parent02f7760e6e5c3d726cd9622749cdae17c571b9a3 (diff)
downloadlinux-dda288d7e4f605632dc6e19c69063f1725056208.tar.xz
arm64: cache: Identify VPIPT I-caches
Add support for detecting VPIPT I-caches, as introduced by ARMv8.2. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cache.h')
-rw-r--r--arch/arm64/include/asm/cache.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 7acb52634299..ea9bb4e0e9bb 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -25,6 +25,7 @@
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
+#define ICACHE_POLICY_VPIPT 0
#define ICACHE_POLICY_VIPT 2
#define ICACHE_POLICY_PIPT 3
@@ -45,6 +46,7 @@
#include <linux/bitops.h>
#define ICACHEF_ALIASING 0
+#define ICACHEF_VPIPT 1
extern unsigned long __icache_flags;
/*
@@ -56,6 +58,11 @@ static inline int icache_is_aliasing(void)
return test_bit(ICACHEF_ALIASING, &__icache_flags);
}
+static inline int icache_is_vpipt(void)
+{
+ return test_bit(ICACHEF_VPIPT, &__icache_flags);
+}
+
static inline u32 cache_type_cwg(void)
{
return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;