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authorMarc Zyngier <marc.zyngier@arm.com>2018-09-27 19:15:32 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2018-10-01 15:36:01 +0300
commit50de013d22e4e112d7b0778a0e7d032f16c46778 (patch)
tree58bcb8f04ccd27b425c6dd86b3aae1e440d7c121 /arch/arm64/include/asm/esr.h
parent2a8905e18c55d5576d7a53da495b4de0cfcbc459 (diff)
downloadlinux-50de013d22e4e112d7b0778a0e7d032f16c46778.tar.xz
arm64: compat: Add CNTVCT trap handler
Since people seem to make a point in breaking the userspace visible counter, we have no choice but to trap the access. We already do this for 64bit userspace, but this is lacking for compat. Let's provide the required handler. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/esr.h')
-rw-r--r--arch/arm64/include/asm/esr.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 56d32e5557a5..5548712ce6e5 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -315,6 +315,9 @@
ESR_ELx_CP15_64_ISS_CRM_MASK | \
ESR_ELx_CP15_64_ISS_DIR_MASK)
+#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
+ ESR_ELx_CP15_64_ISS_DIR_READ)
+
#ifndef __ASSEMBLY__
#include <asm/types.h>