diff options
| author | Mark Brown <broonie@kernel.org> | 2022-09-06 01:54:21 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-09-09 12:59:06 +0300 |
| commit | cea08f2bf406416c9f54366e1328f2ce329bf4fd (patch) | |
| tree | 2ba756ac6e99c775c54785abbd518e1f480b118d /arch/arm64/include/asm/sysreg.h | |
| parent | cfa3a6c55b61a062afa1ccd8bca45fd270dd3d0f (diff) | |
| download | linux-cea08f2bf406416c9f54366e1328f2ce329bf4fd.tar.xz | |
arm64/sysreg: Convert ID_AA64PFR0_EL1 to automatic generation
Automatically generate the constants for ID_AA64PFR0_EL1 as per DDI0487I.a,
no functional changes. The generic defines for the ELx fields are left in
place as they remain useful.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-25-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 62c5c596b18f..2f032ea7e7e8 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -190,7 +190,6 @@ #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) -#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) @@ -681,29 +680,6 @@ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) /* id_aa64pfr0 */ -#define ID_AA64PFR0_EL1_CSV3_SHIFT 60 -#define ID_AA64PFR0_EL1_CSV2_SHIFT 56 -#define ID_AA64PFR0_EL1_DIT_SHIFT 48 -#define ID_AA64PFR0_EL1_AMU_SHIFT 44 -#define ID_AA64PFR0_EL1_MPAM_SHIFT 40 -#define ID_AA64PFR0_EL1_SEL2_SHIFT 36 -#define ID_AA64PFR0_EL1_SVE_SHIFT 32 -#define ID_AA64PFR0_EL1_RAS_SHIFT 28 -#define ID_AA64PFR0_EL1_GIC_SHIFT 24 -#define ID_AA64PFR0_EL1_AdvSIMD_SHIFT 20 -#define ID_AA64PFR0_EL1_FP_SHIFT 16 -#define ID_AA64PFR0_EL1_EL3_SHIFT 12 -#define ID_AA64PFR0_EL1_EL2_SHIFT 8 -#define ID_AA64PFR0_EL1_EL1_SHIFT 4 -#define ID_AA64PFR0_EL1_EL0_SHIFT 0 - -#define ID_AA64PFR0_EL1_AMU_IMP 0x1 -#define ID_AA64PFR0_EL1_SVE_IMP 0x1 -#define ID_AA64PFR0_EL1_RAS_IMP 0x1 -#define ID_AA64PFR0_EL1_RAS_V1P1 0x2 -#define ID_AA64PFR0_EL1_FP_NI 0xf -#define ID_AA64PFR0_EL1_FP_IMP 0x0 -#define ID_AA64PFR0_EL1_AdvSIMD_NI 0xf #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY 0x1 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT 0x2 |