diff options
| author | Mark Brown <broonie@kernel.org> | 2022-05-10 19:12:03 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-05-16 21:50:20 +0300 |
| commit | 0d1322e7ea755b9de4819aa246ebab924b4cefec (patch) | |
| tree | 426e1c495cc8089285ea90ccf8c9efd2293727ac /arch/arm64/include | |
| parent | 9e2c0819ac853d94c927d5d2f59e2ca2b48500b4 (diff) | |
| download | linux-0d1322e7ea755b9de4819aa246ebab924b4cefec.tar.xz | |
arm64/sme: Automatically generate defines for SMCR
Convert SMCR to use the register definition code, no functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220510161208.631259-8-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a2f0759f65b2..cbf03a1f316e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -216,7 +216,6 @@ #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) #define SYS_SMPRI_EL1 sys_reg(3, 0, 1, 2, 4) -#define SYS_SMCR_EL1 sys_reg(3, 0, 1, 2, 6) #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) @@ -571,7 +570,6 @@ #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2) #define SYS_SMPRIMAP_EL2 sys_reg(3, 4, 1, 2, 5) -#define SYS_SMCR_EL2 sys_reg(3, 4, 1, 2, 6) #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) @@ -631,7 +629,6 @@ #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) -#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) @@ -1117,13 +1114,6 @@ #define ZCR_ELx_LEN_WIDTH 4 #define ZCR_ELx_LEN_MASK 0xf -#define SMCR_ELx_FA64_SHIFT 31 -#define SMCR_ELx_FA64_MASK (1 << SMCR_ELx_FA64_SHIFT) - -#define SMCR_ELx_LEN_SHIFT 0 -#define SMCR_ELx_LEN_WIDTH 4 -#define SMCR_ELx_LEN_MASK 0xf - #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ |