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authorMarc Zyngier <marc.zyngier@arm.com>2018-01-02 21:19:39 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2018-01-08 21:45:19 +0300
commit95e3de3590e3f2358bb13f013911bc1bfa5d3f53 (patch)
treeac213453703987064269bb32c3a902d57a6013d9 /arch/arm64/mm
parentd68e3ba5303f7e1099f51fdcd155f5263da8569b (diff)
downloadlinux-95e3de3590e3f2358bb13f013911bc1bfa5d3f53.tar.xz
arm64: Move post_ttbr_update_workaround to C code
We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
-rw-r--r--arch/arm64/mm/context.c9
-rw-r--r--arch/arm64/mm/proc.S3
2 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 1fe71b9fcf35..511bd1e79b69 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -242,6 +242,15 @@ switch_mm_fastpath:
cpu_switch_mm(mm->pgd, mm);
}
+/* Errata workaround post TTBRx_EL1 update. */
+asmlinkage void post_ttbr_update_workaround(void)
+{
+ asm(ALTERNATIVE("nop; nop; nop",
+ "ic iallu; dsb nsh; isb",
+ ARM64_WORKAROUND_CAVIUM_27456,
+ CONFIG_CAVIUM_ERRATUM_27456));
+}
+
static int asids_init(void)
{
asid_bits = get_cpu_asid_bits();
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index bc334588f234..bc86f7ef8620 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -146,8 +146,7 @@ ENTRY(cpu_do_switch_mm)
phys_to_ttbr x0, x2
msr ttbr0_el1, x2 // now update TTBR0
isb
- post_ttbr_update_workaround
- ret
+ b post_ttbr_update_workaround // Back to C code...
ENDPROC(cpu_do_switch_mm)
.pushsection ".idmap.text", "ax"