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| author | Catalin Marinas <catalin.marinas@arm.com> | 2024-03-07 22:05:29 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2024-03-07 22:05:29 +0300 |
| commit | 88f0912253ea47a2bde36e0820f0b9c025d389ad (patch) | |
| tree | fb477daef419d79cc960de26157e5de2a6fc9b69 /arch/arm64/tools | |
| parent | 0c5ade742e91d7bf3a508bf6223deb7410009b6d (diff) | |
| parent | 27f2b9fcddc76d542ac339febf2af55b67f610ca (diff) | |
| download | linux-88f0912253ea47a2bde36e0820f0b9c025d389ad.tar.xz | |
Merge branch 'for-next/stage1-lpa2' into for-next/core
* for-next/stage1-lpa2: (48 commits)
: Add support for LPA2 and WXN and stage 1
arm64/mm: Avoid ID mapping of kpti flag if it is no longer needed
arm64/mm: Use generic __pud_free() helper in pud_free() implementation
arm64: gitignore: ignore relacheck
arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and VARange
arm64: mm: Make PUD folding check in set_pud() a runtime check
arm64: mm: add support for WXN memory translation attribute
mm: add arch hook to validate mmap() prot flags
arm64: defconfig: Enable LPA2 support
arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs
arm64: kvm: avoid CONFIG_PGTABLE_LEVELS for runtime levels
arm64: ptdump: Deal with translation levels folded at runtime
arm64: ptdump: Disregard unaddressable VA space
arm64: mm: Add support for folding PUDs at runtime
arm64: kasan: Reduce minimum shadow alignment and enable 5 level paging
arm64: mm: Add 5 level paging support to fixmap and swapper handling
arm64: Enable LPA2 at boot if supported by the system
arm64: mm: add LPA2 and 5 level paging support to G-to-nG conversion
arm64: mm: Add definitions to support 5 levels of paging
arm64: mm: Add LPA2 support to phys<->pte conversion routines
arm64: mm: Wire up TCR.DS bit to PTE shareability fields
...
Diffstat (limited to 'arch/arm64/tools')
| -rw-r--r-- | arch/arm64/tools/cpucaps | 1 | ||||
| -rw-r--r-- | arch/arm64/tools/sysreg | 8 |
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 63283550c8e8..46ae9252bc3f 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -51,6 +51,7 @@ HAS_STAGE2_FWB HAS_TCR2 HAS_TIDCP1 HAS_TLB_RANGE +HAS_VA52 HAS_VIRT_HOST_EXTN HAS_WFXT HW_DBM diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 508224a0e078..3fc1650a329e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1573,16 +1573,16 @@ Enum 35:32 TGRAN16_2 0b0010 IMP 0b0011 52_BIT EndEnum -Enum 31:28 TGRAN4 +SignedEnum 31:28 TGRAN4 0b0000 IMP 0b0001 52_BIT 0b1111 NI EndEnum -Enum 27:24 TGRAN64 +SignedEnum 27:24 TGRAN64 0b0000 IMP 0b1111 NI EndEnum -Enum 23:20 TGRAN16 +UnsignedEnum 23:20 TGRAN16 0b0000 NI 0b0001 IMP 0b0010 52_BIT @@ -1730,7 +1730,7 @@ Enum 23:20 CCIDX 0b0000 32 0b0001 64 EndEnum -Enum 19:16 VARange +UnsignedEnum 19:16 VARange 0b0000 48 0b0001 52 EndEnum |