diff options
| author | Mark Rutland <mark.rutland@arm.com> | 2022-05-13 20:41:17 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-05-15 12:58:25 +0300 |
| commit | 82bf59002e0f84e51c16589080c2feba6e6ec78a (patch) | |
| tree | 8580e57045f51862266320cee8d3391398105d04 /arch/arm64/tools | |
| parent | 7a41a97b65ea7c4e0458b11e7a2c71c6dd3be0c4 (diff) | |
| download | linux-82bf59002e0f84e51c16589080c2feba6e6ec78a.tar.xz | |
arm64/sysreg: improve comment for regs without fields
Currently for registers without fields we create a comment pointing at
the common definitions, e.g.
| #define REG_TTBR0_EL1 S3_0_C2_C0_0
| #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
| #define SYS_TTBR0_EL1_Op0 3
| #define SYS_TTBR0_EL1_Op1 0
| #define SYS_TTBR0_EL1_CRn 2
| #define SYS_TTBR0_EL1_CRm 0
| #define SYS_TTBR0_EL1_Op2 0
|
| /* See TTBRx_EL1 */
It would be slightly nicer if the comment said what we should be looking
for, e.g.
| #define REG_TTBR0_EL1 S3_0_C2_C0_0
| #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
| #define SYS_TTBR0_EL1_Op0 3
| #define SYS_TTBR0_EL1_Op1 0
| #define SYS_TTBR0_EL1_CRn 2
| #define SYS_TTBR0_EL1_CRm 0
| #define SYS_TTBR0_EL1_Op2 0
|
| /* For TTBR0_EL1 fields see TTBRx_EL1 */
Update the comment generation accordingly.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20220513174118.266966-2-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/tools')
| -rwxr-xr-x | arch/arm64/tools/gen-sysreg.awk | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index 3ffd77cbb499..f41feb87d0ca 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -184,7 +184,7 @@ END { if (next_bit != 63) fatal("Some fields already defined for " reg) - print "/* See " $2 " */" + print "/* For " reg " fields see " $2 " */" print "" next_bit = 0 |