diff options
author | Mark Rutland <mark.rutland@arm.com> | 2021-03-26 21:01:36 +0300 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2021-03-28 20:23:01 +0300 |
commit | 776e49af6000ef95301d0d3f834543bda43cb7fb (patch) | |
tree | b2e141fa254242f1d7922dce307f8404c6cbce18 /arch/arm64 | |
parent | b07f3499661c61f03478c99ff3fcb2381ddb9e38 (diff) | |
download | linux-776e49af6000ef95301d0d3f834543bda43cb7fb.tar.xz |
arm64: setup: name `mair` register
In __cpu_setup we conditionally manipulate the MAIR_EL1 value in x5
before later reusing x5 as a scratch register for unrelated temporary
variables.
To make this a bit clearer, let's move the MAIR_EL1 value into a named
register `mair`. To simplify the register allocation, this is placed in
the highest available caller-saved scratch register, x17. As it is no
longer clobbered by other usage, we can write the value to MAIR_EL1 at
the end of the function as we do for TCR_EL1 rather than part-way though
feature discovery.
There should be no functional change as as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210326180137.43119-2-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/mm/proc.S | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c967bfd30d2b..f560b6fde34c 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -421,7 +421,8 @@ SYM_FUNC_START(__cpu_setup) /* * Memory region attributes */ - mov_q x5, MAIR_EL1_SET + mair .req x17 + mov_q mair, MAIR_EL1_SET #ifdef CONFIG_ARM64_MTE mte_tcr .req x20 @@ -438,7 +439,7 @@ SYM_FUNC_START(__cpu_setup) /* Normal Tagged memory type at the corresponding MAIR index */ mov x10, #MAIR_ATTR_NORMAL_TAGGED - bfi x5, x10, #(8 * MT_NORMAL_TAGGED), #8 + bfi mair, x10, #(8 * MT_NORMAL_TAGGED), #8 /* initialize GCR_EL1: all non-zero tags excluded by default */ mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) @@ -452,7 +453,6 @@ SYM_FUNC_START(__cpu_setup) mov_q mte_tcr, TCR_KASAN_HW_FLAGS 1: #endif - msr mair_el1, x5 /* * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further * adjusted if the kernel is compiled with 52bit VA support. @@ -492,10 +492,13 @@ SYM_FUNC_START(__cpu_setup) orr x10, x10, #TCR_HA // hardware Access flag update 1: #endif /* CONFIG_ARM64_HW_AFDBM */ + msr mair_el1, mair msr tcr_el1, x10 /* * Prepare SCTLR */ mov_q x0, INIT_SCTLR_EL1_MMU_ON ret // return to head.S + + .unreq mair SYM_FUNC_END(__cpu_setup) |